Review of the Machine Cycle

When a program is executing its instructions are located in main memory. The address of an instruction is the address of the first (the lowest addressed) byte of the four-byte instruction.

Each machine cycle executes one machine instruction. At the top of the machine cycle, the PC (program counter) contains the address of an instruction to fetch from memory. The instruction is fetched into the processor and is prepared for execution.

In the middle of the machine cycle the PC is incremented by four so that it points to the instruction that follows the one just fetched. Then the fetched instruction is executed and the cycle repeats. The machine cycle automatically executes instructions in sequence.

The effect of a jump instruction is to put a new address into the PC. Now the fetch at the top of the next machine cycle fetches the instruction at the new address. Instead of executing the instruction that follows the jump instruction in memory, the processor "jumps" to an instruction somewhere else in memory.

However, it takes an extra machine cycle before the change in the PC takes effect. Before the PC changes, the instruction after the jump instruction has been fetched and executed. The instruction that follows a jump instruction in memory is said to be in the branch delay slot.

The reason for this delay is that MIPS is pipelined. Normally instructions are executed in sequence. In order to gain speed, the processor cleverly fetches several sequential instructions and starts working on them all. When the machine cycle calls for one of these instructions to be executed, most of the work has already been done. These instructions are in an instruction pipe.

This means that the instruction after a jump instruction has mostly been completed when the jump is executed. Rather than waste this effort, the instruction is allowed to finish. Only then is the PC changed by the jump instruction.

The instruction that follows a jump instruction in memory (in the branch delay slot) is always executed. After it executes the next instruction to execute is the one that was jumped to. Often the branch delay slot is filled with a no-op instruction.

IMPORTANT: The SPIM simulator allows you to turn the pipeline feature off, but this is not an option with actual R2000 hardware.   To make sure the pipeline feature is turned off (and therefore, do not have to worry about the branch delay slot) select Simulator and then Settings.  You will get a dialog box that looks like:

Make sure the Delayed Branches and Delayed Load boxes are NOT checked.